1. Field
Embodiments of the present disclosure are directed to high density semiconductor devices, such as non-volatile memory, and methods of forming the same.
2. Description of the Related Art
As the size of electronic devices continue to decrease, there is continual pressure to shrink the substrate area required to implement the various integrated circuit functions. Semiconductor memory devices, for example, and the fabrication processes therefore are continuously evolving to meet demands for increases in the amount of digital data that can be stored in a given area of a silicon substrate. Such demands stem from a desire to increase the storage capacity within a memory card while maintaining or even decreasing the card form factor.
As demands for higher densities in integrated circuit applications have increased, fabrication processes have evolved to reduce the minimum feature sizes of circuit elements such as the gate and channel regions of transistors. For example, Choi et al., “Sublithographic Nanofabrication Technology for Nanocatalysts and DNA Chips,” J. Vac. Sci. Technol. B 21(6), November/December 2003, pp. 2951-2955, describes an iterative spacer lithography technique which multiplies the pattern density in an integrated circuit to achieve an element width and a corresponding space therebetween that is smaller than a minimum definable lithographic feature size. Such decreases in the sizes of circuit elements, as well as other considerations, increase the need for precision in fabrication processes and integrity in resulting materials.
It is desirable that the process form features whose width are within design tolerances. Also, the space between the features should be within design tolerances. Typically, the term critical dimension (CD) variation refers to the variation of the width and space from target values. It is desirable to have little CD variation.
It is desirable that the process form features whose locations are within design tolerance. For purposes of discussion, the location of a feature can be considered to be its center with respect to a cross section. For example, for the cross section of a line having a width “W”, the center is at the midpoint of the cross section. For a group of parallel lines, it may be desirable that the center of each line be located at regular intervals. Typically, the term overlay variation refers to the variation of the location of each feature. It is desirable to have low overlay variation.